Comments on: PCEPTPDPTE http://www.pagetable.com/?p=308 Some Assembly Required Thu, 09 Sep 2010 09:36:59 +0000 hourly 1 http://wordpress.org/?v=3.0.1 By: Shang Ling Liao http://www.pagetable.com/?p=308&cpage=1#comment-101049 Shang Ling Liao Thu, 12 Nov 2009 19:56:35 +0000 http://www.pagetable.com/?p=308#comment-101049 Just to complement the topic, here are the names for each register: * AX/EAX/RAX: accumulator * BX/EBX/RBX: base * CX/ECX/RCX: counter * DX/EDX/RDX: data/general * SI/ESI/RSI: "source index" for string operations. * DI/EDI/RDI: "destination index" for string operations. * SP/ESP/RSP: stack pointer for top address of the stack. * BP/EBP/RBP: stack base pointer for holding the address of the current stack frame. * IP/EIP/RIP: instruction pointer. Holds the program counter, the current instruction address. source: http://en.wikipedia.org/wiki/X86#x86_registers Just to complement the topic, here are the names for each register:

* AX/EAX/RAX: accumulator
* BX/EBX/RBX: base
* CX/ECX/RCX: counter
* DX/EDX/RDX: data/general
* SI/ESI/RSI: “source index” for string operations.
* DI/EDI/RDI: “destination index” for string operations.
* SP/ESP/RSP: stack pointer for top address of the stack.
* BP/EBP/RBP: stack base pointer for holding the address of the current stack frame.
* IP/EIP/RIP: instruction pointer. Holds the program counter, the current instruction address.

source: http://en.wikipedia.org/wiki/X86#x86_registers

]]> By: b* http://www.pagetable.com/?p=308&cpage=1#comment-101028 b* Sun, 01 Nov 2009 11:54:52 +0000 http://www.pagetable.com/?p=308#comment-101028 Brilliant and fun! :D Brilliant and fun! :D

]]> By: Tom http://www.pagetable.com/?p=308&cpage=1#comment-101025 Tom Sat, 31 Oct 2009 20:20:15 +0000 http://www.pagetable.com/?p=308#comment-101025 Nice, although this is slightly incorrect, and even comment in VirtualBox is wrong! Intel defines the four levels as PML4, PDPT, PD, PT and thus the entries at those levels respectively are PML4E, PDPTE, PDE, PTE so an EPTPDPTE is an entry in level 3 of the nested page table, i.e. an EPT Page Directory Pointer Table Entry. Clearly this is only going get more awesome when Intel decides that 48bits of virtual address isn't enough and comes up with a name for the 5th level. Nice, although this is slightly incorrect, and even comment in VirtualBox is wrong! Intel defines the four levels as

PML4, PDPT, PD, PT

and thus the entries at those levels respectively are

PML4E, PDPTE, PDE, PTE

so an EPTPDPTE is an entry in level 3 of the nested page table, i.e. an EPT Page Directory Pointer Table Entry. Clearly this is only going get more awesome when Intel decides that 48bits of virtual address isn’t enough and comes up with a name for the 5th level.

]]> By: SĂŠbastien Duquette http://www.pagetable.com/?p=308&cpage=1#comment-101024 SĂŠbastien Duquette Sat, 31 Oct 2009 16:39:39 +0000 http://www.pagetable.com/?p=308#comment-101024 LOL. But seriously, how can one not go batshit after extended exposition to this kind of non-sense. LOL. But seriously, how can one not go batshit after extended exposition to this kind of non-sense.

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