Monthly Archives: October 2009


Here is a new pagetable entry.

I like Intel. I told you before how Intel messed up the x86 register nomenclature by extending A to AX (A extended) and then to EAX (extended A extended). Then AMD came and extended the register once more, giving it a more sane name: RAX.

I also told you before how Intel messed up the x86 pagetable nomenclature: There were pagetables (PT, level 1) and page directories (PD, level 2) on the i386, and for the Pentium Pro, they added page directory pointers (PDP, level 3). Then AMD came and extended it once more, giving it a more sane name: page map level 4 (PML4).

With the advent of virtualization, both Intel and AMD added a feature to get rid of the slow software shadow pagetables, and added hardware support for nested pagetables, i.e. the guest has 4 levels of pagetables, and the host has another 4 levels.

AMD called these – surprise, surprise! – nested pagetables, NPT. Intel was more creative. With a history of extending architectures, they went with the big E: extended pagetables, EPT.

Let’s practice a bit: A PD is a page directory, a PDE is a page directory entry. You can also call it a PDPTE, a page directory pagetable entry (level 2 PTE), because after all, all these entries on all levels are PTEs, because they share the same format. A PDPPTE is a page directory pointer pagetable entry, aka level 3 entry.

If we use nested paging – excuse me – extended paging on Intel, we need to prepend EPT to our nice little abbreviations. An EPTPTE is a level 1 entry, an EPTPDPTE is level 2 not to be confused with an EPTPDPPTE, which is level 3, and a level 4 entry is EPTPML4PTE.

It get even better. Oracle/Sun/Innotek VirtualBox uses Hungarian Notation for its variable names, so it prepends “P” for pointer and “C” for constant. So what would you call a variable, which is a pointer to a constant level 2 EPT entry?

Of course, PCEPTPDPTE.

/** Pointer to a const EPT Page Directory Pointer Entry. */

I thought about this for a while, and considered patenting this brilliant idea of mine, but here it is, free of patents and free for everyone to use: Michael’s nomenclature for Intel/AMD pagetables:

new name description old name
P4 pagetable level 4 page PML4
P3 pagetable level 3 page PDP
P2 pagetable level 2 page PD
P1 pagetable level 1 page PT
P4E pagetable level 4 entry PML4E/PML4PTE
P3E pagetable level 3 entry PDPE/PDPPTE
P2E pagetable level 2 entry PDE/PDPTE
P1E pagetable level 1 entry PTE
NP4 nested pagetable level 4 page EPTPML4
NP3 nested pagetable level 3 page EPTPDP
NP2 nested pagetable level 2 page EPTPD
NP1 nested pagetable level 1 page EPTPT
NP4E nested pagetable level 4 entry EPTPML4E/EPTPML4PTE
NP3E nested pagetable level 3 entry EPTPDPE/EPTPDPPTE
NP2E nested pagetable level 2 entry EPTPDE/EPTPDPTE
NP1E nested pagetable level 1 entry EPTPTE

You are welcome.