{"id":1798,"date":"2025-05-08T14:17:06","date_gmt":"2025-05-08T12:17:06","guid":{"rendered":"https:\/\/www.pagetable.com\/?p=1798"},"modified":"2025-05-13T15:16:54","modified_gmt":"2025-05-13T13:16:54","slug":"6502-illegal-opcodes-in-the-siemens-pc-100-assembly-manual-1980","status":"publish","type":"post","link":"https:\/\/www.pagetable.com\/?p=1798","title":{"rendered":"6502 Illegal Opcodes in the Siemens PC 100 Assembly Manual (1980)"},"content":{"rendered":"

The 6502’s “illegal” opcodes<\/a> were of intense interest to home computer enthusiasts, and analyses were published in various<\/a> magazines<\/a>. But one would have never expected a company like Siemens to document illegal opcodes in a programming manual from 1980.<\/p>\n

The PC 100 Assembly Manual<\/h2>\n

The Siemens PC 100 is basically a Rockwell AIM-65 single-board computer in a case, featuring a 6502 processor, integrated keyboard, LED display, and thermal printer, tailored for educational and development purposes with localized documentation and modified ROMs.<\/p>\n

Siemens’ German-language manuals were largely based on Rockwell’s originals, but shuffled the contents. Of particular interest is the assembly manual:<\/p>\n

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Siemens Assembler-Handbuch Personal-Computer PC 100, Ausgabe 1980\/1981<\/a>
(124 pages, 17 MB)<\/a><\/p>\n

It consists of:<\/p>\n\n\n\n\n\n\n\n\n
Assembler-Handbuch <\/th>\n Rockwell <\/th>\n Description <\/th>\n<\/tr>\n<\/thead>\n
Chapters 1\u20139 <\/td>\n User’s Guide, Chapter 5<\/a> <\/td>\n Assembler Reference <\/td>\n<\/tr>\n
Chapter 10 <\/td>\n Programming Manual, Appendix B<\/a> <\/td>\n 6502 Reference <\/td>\n<\/tr>\n
Chapter 11 <\/td>\n User’s Guide, Chapter 3<\/a> <\/td>\n Monitor Reference <\/td>\n<\/tr>\n
Chapter 12 <\/td>\n \u2013 <\/td>\n Tables <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

“Special Instructions”<\/h2>\n

The 6502 Reference has three extra pages at the end describing “Sonderbefehle” (“special instructions”) that were not in the original MOS\/Rockwell 6502 reference that this chapter is a translation of. We can assume this was original research by Siemens.<\/p>\n

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\n\"\"
\n\"\"<\/p>\n

Here is the translated transcription:<\/p>\n

<\/p>\n

10.3 Special Instructions<\/strong><\/p>\n

The microprocessor recognizes a number of special instructions that are largely unknown but can provide valuable assistance to the user in program development. The chosen mnemonics in the following tables are merely recommendations for effectively representing these instructions.<\/p>\n

Note:<\/em>
\nThese instructions are not part of the specification and may be changed at any time without notice. The special commands cannot be decoded by the assembler program and must be programmed using the .BYT directive (see Chapter 10.2).<\/em><\/p>\n

AAX<\/strong> Logical “AND” operation between the accumulator and X-register, with result storage.<\/p>\n

Operation<\/strong> A \u2227 X \u2192 M with Zero Page und (A) \u2227 X \u2227 $02 \u2192 M with Absolute<\/p>\n

Flags<\/strong><\/p>\n\n\n\n\n\n
N <\/th>\n Z <\/th>\n C <\/th>\n I <\/th>\n D <\/th>\n V <\/th>\n<\/tr>\n<\/thead>\n
\u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n\n\n
Addressing Mode <\/th>\n Assembler Mnemonic <\/th>\n OP CODE <\/th>\n No. Bytes <\/th>\n<\/tr>\n<\/thead>\n
Zero Page <\/td>\n AAX Oper <\/td>\n 87 <\/td>\n 2 <\/td>\n<\/tr>\n
Zero Page, Y <\/td>\n AAX+16 Oper <\/td>\n 97 <\/td>\n 2 <\/td>\n<\/tr>\n
X-Reg. \u2227 $02
Absolute <\/td>\n		 AAX+23 Oper <\/td>\n 9E <\/td>\n 3 <\/td>\n<\/tr>\n
X-Reg. \u2227 Accu \u2227 $02
Absolute <\/td>\n		 AAX+24 Oper <\/td>\n 9F <\/td>\n 3 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

DCM<\/strong> Decrement memory location by one and compare result with accumulator.<\/p>\n

Operation<\/strong> M – 1 \u2192 M and A – M<\/p>\n

Flags<\/strong><\/p>\n\n\n\n\n\n
N <\/th>\n Z <\/th>\n C <\/th>\n I <\/th>\n D <\/th>\n V <\/th>\n<\/tr>\n<\/thead>\n
V <\/td>\n V <\/td>\n V <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n
Addressing Mode <\/th>\n Assembler Mnemonic <\/th>\n OP CODE <\/th>\n No. Bytes <\/th>\n<\/tr>\n<\/thead>\n
Zero Page <\/td>\n DCM Oper <\/td>\n C7 <\/td>\n 2 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

LAX<\/strong> Load accumulator and X register<\/p>\n

Operation<\/strong> M \u2192 A and M \u2192 X<\/p>\n

Flags<\/strong><\/p>\n\n\n\n\n\n
N <\/th>\n Z <\/th>\n C <\/th>\n I <\/th>\n D <\/th>\n V <\/th>\n<\/tr>\n<\/thead>\n
V <\/td>\n V <\/td>\n – <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n\n
Addressing Mode <\/th>\n Assembler Mnemonic <\/th>\n OP CODE <\/th>\n No. Bytes <\/th>\n<\/tr>\n<\/thead>\n
Immediate <\/td>\n LAX Oper <\/td>\n AB <\/td>\n 2 <\/td>\n<\/tr>\n
Zero Page <\/td>\n LAX-4 Oper <\/td>\n A7 <\/td>\n 2 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

ISB<\/strong> Increment memory cell by one and subtract result from accumulator<\/p>\n

Operation<\/strong> M + 1 \u2192 M and A – M \u2192 A<\/p>\n

Flags<\/strong><\/p>\n\n\n\n\n\n
N <\/th>\n Z <\/th>\n C <\/th>\n I <\/th>\n D <\/th>\n V <\/th>\n<\/tr>\n<\/thead>\n
V <\/td>\n V <\/td>\n V <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n \u2013 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n\n\n\n
Addressing Mode <\/th>\n Assembler Mnemonic <\/th>\n OP CODE <\/th>\n No. Bytes <\/th>\n<\/tr>\n<\/thead>\n
Zero Page <\/td>\n ISB Oper <\/td>\n E7 <\/td>\n 2 <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Note:<\/em>
\nThe instructions LAX Immediate, AAX X reg $02 and AAX X reg accu $02 are not always processed correctly.<\/em><\/p>\n

10.4 Programming in Assembly Language<\/strong><\/p>\n

Since the special instructions mentioned above cannot be decoded by the assembler program, they must be programmed using the .BYT directive.<\/p>\n<\/div>\n

Analysis<\/h2>\n\n\n\n\n\n\n\n\n\n\n
Opcodes <\/th>\n Siemens
Mnemonic <\/th>\n		 Modern
Mnemonic <\/th>\n		 Comment <\/th>\n<\/tr>\n<\/thead>\n
87\/97 <\/td>\n AAX <\/td>\n SAX <\/td>\n Correct. Also exists with izx\/abs addressing modes. <\/td>\n<\/tr>\n
9E\/9F <\/td>\n AAX <\/td>\n SHX\/SHA<\/td>\n It’s aby, not abs. Also, their constant ($02) is actually the high-byte of the instruction address. (It should not be grouped with the other “AAX” opcodes.) <\/td>\n<\/tr>\n
C7 <\/td>\n DCM <\/td>\n DCP <\/td>\n Correct. Also exists with zpx\/izx\/izy\/abs\/abx\/aby addressing modes. <\/td>\n<\/tr>\n
AB <\/td>\n LAX <\/td>\n LAX <\/td>\n Basically correct. The documented unstability comes from bits of the A register sometimes bleeding into the calculation. (More info<\/a>) <\/td>\n<\/tr>\n
A7 <\/td>\n LAX <\/td>\n LAX <\/td>\n Correct. Also exists with zpy\/izx\/izy\/abs\/aby addressing modes. <\/td>\n<\/tr>\n
E7 <\/td>\n ISB <\/td>\n ISC <\/td>\n Correct. Also exists zpx\/izx\/izy\/abs\/abx\/aby addressing modes. <\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

All in all:<\/p>\n