{"id":24,"date":"2006-09-03T14:23:12","date_gmt":"2006-09-03T22:23:12","guid":{"rendered":"http:\/\/www.pagetable.com\/?p=24"},"modified":"2006-09-03T14:23:12","modified_gmt":"2006-09-03T22:23:12","slug":"strange-sse3-opcodes","status":"publish","type":"post","link":"https:\/\/www.pagetable.com\/?p=24","title":{"rendered":"Strange SSE3 opcodes"},"content":{"rendered":"<p>Intel used some strange opcodes for the SSE3 instructions. All MMX\/SSE opcodes use the 0x0f prefix (former &#8220;pop cs&#8221;). They soon noticed the the 0x0f area gets full, so they used the 0x66, 0xf2, 0xf3 prefix as modifiers. The basic rule is:<\/p>\n<ul>\n<li>0x66: makes MMX-intructions use the xmm registers; for SSE instructions this switches from packed single to packed double<\/li>\n<li>0xf3: for SSE-instructions: use the scalar single form<\/li>\n<li>0xf2: for SSE-instructions: use the scalar double form<\/li>\n<\/ul>\n<p>The isn&#8217;t always 100% correct, so you need different tables for 0xf2, 0xf3 form anyway, when writing a disassembler. Example<\/p>\n<ul>\n<li>0fdb: pand mmx, mmx<\/li>\n<li><strong>66<\/strong>0fdb: pand xmm, xmm<\/li>\n<li>0f58: addps<\/li>\n<li><strong>66<\/strong>0f58: addpd<\/li>\n<li><strong>f3<\/strong>0f58: addss<\/li>\n<li><strong>f2<\/strong>0f58: addsd<\/li>\n<\/ul>\n<p>But some of the SSE3 instructions (addsubps, addsubpd, haddps, haddpd, hsubps, haddps) just seem to be placed at random. By the scheme above, one would expect that addsubps\/d share the same opcode and you switch between them with the 0x66 prefix. But they used:<\/p>\n<ul>\n<li><strong>f2<\/strong>0fd0.. addsubps<\/li>\n<li><strong>66<\/strong>0fd0.. addsubpd<\/li>\n<li>0fd0 and <strong>f3<\/strong>0fd0 are both invalid<\/li>\n<\/ul>\n<p>When I first saw this, I thought this is just an error in the tables. Do you have an idea why they didn&#8217;t used 0fd0 for addsubps and 660fd0 for addsubpd?<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Intel used some strange opcodes for the SSE3 instructions. All MMX\/SSE opcodes use the 0x0f prefix (former &#8220;pop cs&#8221;). They soon noticed the the 0x0f area gets full, so they used the 0x66, 0xf2, 0xf3 prefix as modifiers. The basic rule is: 0x66: makes MMX-intructions use the xmm registers; for SSE instructions this switches from &#8230; <a title=\"Strange SSE3 opcodes\" class=\"read-more\" href=\"https:\/\/www.pagetable.com\/?p=24\" aria-label=\"Read more about Strange SSE3 opcodes\">Read more<\/a><\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[33,38],"tags":[],"class_list":["post-24","post","type-post","status-publish","format-standard","hentry","category-trivia","category-x86"],"_links":{"self":[{"href":"https:\/\/www.pagetable.com\/index.php?rest_route=\/wp\/v2\/posts\/24","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.pagetable.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.pagetable.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.pagetable.com\/index.php?rest_route=\/wp\/v2\/users\/3"}],"replies":[{"embeddable":true,"href":"https:\/\/www.pagetable.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=24"}],"version-history":[{"count":0,"href":"https:\/\/www.pagetable.com\/index.php?rest_route=\/wp\/v2\/posts\/24\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.pagetable.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=24"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.pagetable.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=24"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.pagetable.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=24"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}